Currently, increases in the switching speed of logic circuits is largely dictated by enhancements through device scaling for high drive currents, and low-k dielectrics, i.e., dielectrics having a dielectric constant of 4.0 or less, for reduced parasitic capacitance. With advancements in scaling reaching their technical limits, new approaches are desired to increase device performance.
One approach that has been utilized to increase the metal oxide semiconductor field effect transistor (MOSFET) device current has been through the use of semiconductor on insulator (SOI) technology, which allows for a higher drive current through mechanisms, such as the floating body effect, reduced parasitic capacitance, and device isolation. One disadvantage on the above approach is the cost of SOI substrates. Additionally, MOSFETs formed on SOI substrates present a strong history effect that can result in a delay between the first switch and the second switch.